A CMOS imager circuit includes a focal plane array of pixel cells, each one of the cells including a photosensor, for example, a photogate, photoconductor or a photodiode within a substrate for accumulating photo-generated charge in the substrate. Each pixel cell has a charge storage region, formed on or in the substrate, which is connected to the gate of an output transistor that is part of a readout circuit. The charge storage region may be constructed as a floating diffusion region. In some imager circuits, each pixel may include at least one electronic device such as a transistor for transferring charge from the photosensor to the storage region and one device, also typically a transistor, for resetting the storage region to a predetermined charge level prior to charge transference.
In a CMOS imager, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) resetting the storage region to a known state; (4) transfer of charge to the storage region accompanied by charge amplification; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge. Photo charge may be amplified when it moves from the initial charge accumulation region to the storage region. The charge at the storage region is typically converted to a pixel output voltage by a source follower output transistor.
CMOS imagers of the type discussed above are generally known as discussed, for example, in U.S. Pat. Nos. 6,140,630, 6,376,868, 6,310,366, 6,326,652, 6,204,524 and 6,333,205, assigned to Micron Technology, Inc., which are hereby incorporated by reference in their entirety.
A typical four transistor (4T) CMOS imager pixel 10 is shown in FIG. 1. The pixel 10 includes a photosensor 12 (e.g., photodiode, photogate, etc.), transfer transistor 14, floating diffusion region FD, reset transistor 16, source follower transistor 18 and row select transistor 20. The photosensor 12 is connected to the floating diffusion region FD by the transfer transistor 14 when the transfer transistor 14 is activated by a transfer gate control signal TX.
The reset transistor 16 is connected between the floating diffusion region FD and an array pixel supply voltage Vaa_pix. A reset control signal RST is used to activate the reset transistor 16, which resets the floating diffusion region FD to the array pixel supply voltage Vaa_pix level as is known in the art.
The source follower transistor 18 has its gate connected to the floating diffusion region FD and is connected between the array pixel supply voltage Vaa_pix and the row select transistor 20. The source follower transistor 18 converts the charge stored at the floating diffusion region FD into an electrical output voltage signal Vout. The row select transistor 20 is controllable by a row select signal SEL for selectively connecting the source follower transistor 18 and its output voltage signal Vout to a column line 22 of a pixel array.
The signals output from the pixel 10 are analog voltages representing a reset signal Vrst (generated when the floating diffusion region FD is reset) and a pixel output signal Vsig generated after charge from the photosensor 12 is transferred to the floating diffusion region FD. The output signals must be converted from analog to digital for further processing. Due to a typically low capacitance on the floating diffusion region FD, the kT/C noise on Vrst can be excessive. When transferring the charge from photosensor 12 to the floating diffusion region FD, this charge is ideally noiseless and is subtracted from the Vrst signal to produce the Vsig signal. Thus, the pixel output signals Vrst, Vsig are usually sent to a sample and hold circuit and then to a differencing circuit, which forms the signal Vrst-Vsig. This difference signal is then sent to an analog-to-digital converter (ADC) (not shown in FIG. 1).
FIG. 2a illustrates a conventional sigma-delta sensing circuit 50 that could be used as part of a sigma-delta analog-to-digital converter. The sensing circuit 50 comprises a first branch 51 for sensing the reset signal Vrst from a sample and hold capacitor (not shown), and a second branch 61 for sensing the pixel signal Vsig from another sample and hold capacitor (not shown). The sensing circuit 50 also comprises a current mirror 80, a comparator 70 and a NAND gate 72. The comparator 70 may be a regenerative latch type, where the digital output is synchronized to the phase clocks. Smoothing capacitors (not shown) may also be added to the source follower outputs to convert the switching nature of the currents through all branches 51, 61 into near-DC currents for the source follower.
The first branch 51 comprises three PMOS transistors 52, 54, 56 and a capacitor 58. The first PMOS transistor 52 is connected between a supply voltage Vaa and a source/drain terminal of the second PMOS transistor 54. The gate of the first PMOS transistor 52 is connected to a first clock signal /PHI1. The second PMOS transistor 54 has a second source/drain terminal connected to a source/drain terminal of the third PMOS transistor 56. The gate of the second PMOS transistor 54 is connected to a second clock signal /PHI2. The capacitor 58 is connected between a ground potential and the connection between the first and second PMOS transistors 52, 54.
The second source/drain terminal of the third PMOS transistor 56 is connected to a source/drain terminal of a first NMOS transistor 82 of the current mirror 80. The gate of the third PMOS transistor 56 is connected to receive the reset signal Vrst; the third PMOS transistor 56 acts as a source follower transistor for the first branch 51. The second source/drain of the third PMOS transistor 56 is also coupled to a first input of the comparator 70.
In operation, the first clock signal /PHI1 is applied to the gate of the first PMOS transistor 52 and the second clock signal /PHI2 is applied to the gate of the second PMOS transistor 54 in a complementary non-overlapping fashion and at a specified frequency. The designations “/PHI1”and “/PHI2”are used to mean the inverted clock signal of non-overlapping clocks PHI1 and PHI2, respectively. Thus, /PHI1 and /PHI2 cannot be low at the same time. The clock signals /PHI1, /PHI2 are typically generated by a clock generator or control circuit. The two PMOS transistors 52, 54 act as switches under the control of their respective clock signals /PHI1, /PHI2. Activating the first PMOS transistor 52 (i.e., closing the switch by setting /PHI1 low) immediately after deactivating the second PMOS transistor 54 (i.e., opening the switch by setting /PHI2 high) will charge the capacitor 58. Similarly, deactivating the first PMOS transistor 52 (i.e., opening the switch) immediately before activating the second PMOS transistor 54 (i.e., closing the switch) will discharge the capacitor 58.
Using the non-overlapping complementary clock signals /PHI1, /PHI2 to open and close the “switches” (i.e., transistors 52, 54) causes the capacitor 58 to simulate a resistor (e.g., resistor Ri in FIG. 2b). The equivalent resistance of the resistor Ri is equal to 1/f·C, where C is the capacitance of the capacitor 58 and f is the frequency of the clock signals /PHI1, /PHI2. By varying the frequency f, the resistance may be adjusted as desired. For example, the larger the frequency f, the smaller the resistance. The changing of the resistance of the capacitor 58 is referred to as “modulating” the resistance. A reset current IR based on the resistance of the first branch 51 and the reset voltage Vrst flows through the first branch 51 to the comparator 70.
The second branch 61 comprises three PMOS transistors 62, 64, 66 and a capacitor 68. The fourth PMOS transistor 62 is connected between the supply voltage Vaa and a source/drain terminal of the fifth PMOS transistor 64. The gate of the fourth PMOS transistor 62 is connected to the first clock signal /PHI1. The fifth PMOS transistor 64 has a second source/drain terminal connected to a source/drain terminal of the sixth PMOS transistor 66. The gate of the fifth PMOS transistor 64 is connected the output of the NAND gate 72. The second capacitor 68 is connected between a ground potential and the connection between the fourth and fifth PMOS transistors 62, 64.
The second source/drain terminal of the sixth PMOS transistor 66 is connected to a source/drain terminal of a second NMOS transistor 84 of the current mirror 80. The gate of sixth PMOS transistor 66 is connected to receive the pixel signal Vsig; the sixth PMOS transistor 66 acts as a source follower transistor for the second branch 61. The second source/drain of the sixth PMOS transistor 66 is also coupled to a second input of the comparator 70. The output of the comparator 70 is connected to a first input of the NAND gate 72. The non-inverted second clock signal PHI2 is connected to a second input of the NAND gate 72.
In operation, the first clock signal /PHI1 is applied to the gate of the fourth PMOS transistor 62. The output of the NAND gate 72, which is essentially clocked by the non-inverted second clock signal PHI2, is applied to the gate of the fifth PMOS transistor 64. As set forth above, the clock signals /PHI1, /PHI2 are non-overlapping complementary signals. The two PMOS transistors 62, 64 act as switches, where the fourth PMOS transistor 62 is controlled by the first clock signal /PHI1 and the fifth PMOS transistor 64 is controlled by the output of the NAND gate 72 (as clocked by PHI2). Activating the fourth PMOS transistor 62 (i.e., closing the switch) immediately after deactivating the fifth PMOS transistor 64 (i.e., opening the switch) will charge the capacitor 68. Similarly, deactivating the fourth PMOS transistor 62 (i.e., opening the switch) immediately before activating the fifth PMOS transistor 64 (i.e., closing the switch) will discharge the capacitor 68.
Using the non-overlapping complementary clock signals /PHI1, /PHI2 (and the output of the comparator 70) to open and close the “switches” (i.e., transistors 62, 64) causes the capacitor 68 to simulate a resistor (e.g., resistor Rx in FIG. 2b) with an equivalent resistance equal to 1/f·C, where C is the capacitance of the capacitor 68 and f is the average frequency of the clock signal output from the NAND gate 72. As set forth above, by varying the frequency f, the resistance may be adjusted or modulated as desired. A pixel signal current IS based on the resistance of the second branch 61 and the Vsig voltage level flows through the second branch 61 to the comparator 70.
The operation of the sensing circuit is now explained in more detail with reference to FIG. 2b. FIG. 2b illustrates a conventional sigma-delta analog-to-digital converter 100 using the FIG. 2a sigma-delta sensing circuit 50. Portions of the sensing circuit 50 illustrated in FIG. 2a have been replaced by their functional equivalents in FIG. 2b. For example, in FIG. 2b, a first resistor Ri replaces the first switched capacitor 58 and the first and second PMOS transistors 52, 54 shown in FIG. 2a. Likewise, in FIG. 2b, a second resistor Rx, shown as an adjustable resistor, replaces the second switched capacitor 68 and the fourth and fifth PMOS transistors 62, 64 shown in FIG. 2a. The NAND gate 72 is also not shown in FIG. 2b. The analog-to-digital converter 100 also includes a counter 90 connected to the output of the comparator 70.
The sensing circuit 50, and as such, the analog-to-digital converter 100, operates based on a sigma-delta modulation approach. In principle, the sensing circuit 50 attempts to get the reset signal current IR and the pixel signal current IS to be the same. Since typically it is most likely that the reset signal voltage Vrst will be larger than the pixel signal voltage Vsig, the sensing circuit 50 needs to modulate the resistance of one of the branches 51, 61 to maintain identical IR and IS currents. In the illustrated example, the sensing circuit 50 can increase the resistance Rx associated with the switched capacitor 68 (FIG. 2a) of the second branch 61 by occasionally skipping clocks to the gate of PMOS transistor 64. The counter 90 keeps track of the number, M, of times the resistance Rx is adjusted over a predetermined number of clock cycles N. The number of clock cycles N is typically equal to 2n, where n is the number of bits of resolution in the analog-to-digital converter 100. The number M of times the resistance Rx is changed, can be used by the counter 90 to generate a digital code ADC CODE corresponding to the actual light impinging on the pixel.
The operation of the sensing circuit 50 can be expressed by the following current equations:(Vaa−Vsig−Vtp66)/Rx=(Vaa−Vrst−Vtp56)/Ri,  (1)where Vtp66 is the threshold voltage of the sixth PMOS transistor 66 and Vtp56 is the threshold voltage of the third PMOS transistor 56. This equation becomes:(Vaa−Vsig−Vtp66)=(Vaa−Vrst−Vtp56)·Rx/Ri  (2)
It is known that the ratio of the resistance Ri to resistance Rx is inversely proportional to the number, M, of times the resistance Rx is adjusted over a predetermined number of clock cycles N. As such, equation (2) becomes:Ri/Rx=M/N=(Vaa−Vrst−Vtp56)/(Vaa−Vsig−Vtp66)  (3)
Although the sigma-delta sensing circuit 50 and the sigma-delta analog-to-digital converter 100 operate effectively to produce a digital code ADC CODE representing the light impinging on a pixel, they are not without their shortcomings. For example, as shown in the above equations, the output code ADC CODE is essentially based on the ratio of the Vsig and Vrst voltages. These voltages, however, may have been adversely impacted by noise during the readout and/or sample and hold operations, which is stored in the Vrst and Vsig signals. This noise, therefore, factors into the operation of the sensing circuit 50 (and the analog-to-digital converter 100), which may cause undesirable results.
Thus, it is desirable to mitigate noise from the sigma-delta modulation sensing circuit 50 and analog-to-digital converter 100 to achieve more accurate results. It is also desirable to implement gain control within the sigma-delta modulation sensing circuit 50 and analog-to-digital converter 100.